1. Field of the Invention
The present invention relates to a package substrate for a semiconductor device in which integrated circuit elements are mounted, to a method of fabricating the package substrate, and to a semiconductor device that includes the package substrate for a semiconductor device.
2. Description of the Related Art
Packages are conventionally used for incorporating integrated circuit elements such as LSI chips and connecting the integrated circuit elements to what is called a “motherboard” (circuit board). Such a package incorporates a multilayer board on which various signal lines, ground patterns, and power-supply patterns have been formed. The integrated circuit elements and motherboard are connected by way of this multilayer board.
Multilayer boards for packaging of the prior art include the built-up type of multilayer board that is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-158671 (see FIG. 1). In a built-up multilayer board, substrate layers (layers of an organic material composed of, for example, epoxy resin) 102 composed of, for example, prepreg are successively laminated on both sides of thick core material 101 that serves as a base. An actual method of fabricating a built-up multilayer board is as follows: First, a thermosetting epoxy resin is impregnated in a glass cloth and cured to form core material 101 that is composed of glass epoxy resin. This core material 101 is of a multilayer construction having internal copper foil layers as necessary. Conductive patterns are formed of copper foil on both sides of core material 101, and through-holes 103 that pass through core material 101 are formed to interconnect the conductive patterns on the two sides of core material 101. Through-holes 103 are formed by opening holes in core material 101 by laser irradiation or by a drill and then depositing a metal layer by plating the interior walls of these through-holes. Causing portions of this metal layer to contact each of the conductive patterns on both sides of core material 101 electrically connects the conductive patterns on the two sides of core material 101.
Multilayering is realized by successively forming (building up) a plurality of substrate layers 102 of prepreg having conductive patterns 105 that are composed of, for example, copper foil on core material 101 that has been formed in this way. Through-holes are formed in substrate layers 102 in the direction of thickness, and vias 104 are formed by embedding metal in these through-holes. Vias 104 connect conductive patterns 105 that are located on the upper layers of substrate layers 102 and conductive patterns 105 that are located on the lower layers. By this method, a plurality of layers of substrate layers 102 that are composed of, for example, a prepreg and conductive patterns 105 that are formed of, for example, copper foil are formed on both sides of core material 101, and each layer of these conductive patterns 105 are connected by vias 104 to form a multilayer board.
In the configuration that is disclosed in Japanese Patent Laid-Open Publication No. 2004-158671, in contrast to the configuration that is shown in FIG. 1, conductive patterns 105 on the both sides of substrate layer 102 are connected by forming through-holes in substrate layer 102 that are similar to the through-holes in core material 101.
Another package substrate of the prior art is a multilayer board in which a multiplicity of ceramic layers are laminated (see FIG. 2) as disclosed in the Japanese Patent Laid-Open Publication No. 2002-118194. As the actual method of fabricating this multilayer board, a metal such as silver or tungsten is printed on a presintering sheet called a “green sheet” to form conductive patterns 106. Through-holes are next formed at prescribed positions of the green sheet by laser irradiation or punching, and metal is embedded in these through-holes to form vias 107. Vias 107 connect conductive patterns 106 that are located on the upper layers of the green sheet and conductive patterns 106 that are located on the lower layers. After stacking a multiplicity of green sheets in which conductive patterns 106 and vias 107 have been formed in this way, the green sheets are sintered to cure the green sheets all at one time. In this way, a multilayer board can be formed from ceramic 108.
The following explanation regards an example of a configuration that employs a multilayer board described above as the package substrate for a semiconductor device. A plurality of connection terminals 110 are provided on one of the outermost layers of a multilayer board for electrically connecting with solder bumps 116 when mounting integrated circuit elements 109 of the flip-chip connection type, these connection terminals 110 being exposed to the outside. A plurality of metal pads 111 are provided on the outermost layer on the opposite side of this multilayer board, and solder balls (ball terminals) 112 are mounted and secured on these metal pads 111. A ball grid array (BGA) structure for connecting with a motherboard is thus formed. In this way, a package substrate for a semiconductor device can be completed.
Japanese Patent Application Laid-Open No. 2000-038464 discloses a printed wiring board in which conductive patterns are formed on the surfaces of film insulators composed of polyarylketone and polyetherimide, and these film insulators are then laminated in a plurality of layers.
The built-up multilayer board such as disclosed in the example of Japanese Patent Application Laid-Open No. 2004-158671 involves the formation of core material 101 followed by the successive formation of a plurality of substrate layers 102 and therefore necessitates an extremely time-consuming fabrication process and high fabrication costs. For example, this method is inefficient and impractical when fabricating a multilayer board having ten or more layers, and in particular, thirteen or more layers.
According to Japanese Patent Application Laid-Open No. 2004-158671, core material 101 must have sufficient strength and thickness for the laminated formation of a multiplicity of substrate layers 102. Core material 101 formed from only epoxy resin would therefore have insufficient strength, and a multilayer construction incorporating metal layers and further incorporating glass cloth is therefore adopted to obtain sufficient strength. However, the adoption of core material 101 having a multilayer construction is not preferable due to the further increase in fabrication time and fabrication costs. In addition, the incorporation of glass cloth in core material 101 raises the concern that penetration by moisture might lead to the occurrence of dendrites. To prevent the problem of dendrites, the pitch between through-holes 103 must be made at least 0.80 mm. This requirement interferes with the high-density wiring and prevents an adequate response to the demand for a more compact semiconductor device package.
In addition, because core material 101 is thick, the formation of vias by embedding metal in through-holes becomes problematic due to the difficulty of the fabrication steps and the amount of metal material that must be used. The inner circumference of through-holes is therefore covered by metal foil to form through-holes 103. In other words, the through-holes have a structure that is not filled, and vias 104 therefore cannot be formed directly above and directly below through-holes 103. The arrangement of a multiplicity of vias 104 in a direct line in the direction of thickness is therefore physically impossible due to the interposition of the locations of the holes of through-holes 103. As a result, vias 104 of each layer cannot all be formed in the same planar positions, but must be shifted within the plane. As a result, the connection of a multiplicity of layers of conductive patterns 105 on one surface of core material 101 to a multiplicity of layers of conductive patterns 105 on the other surface cannot be realized with good space efficiency. This construction therefore suffers from the problem of poor freedom degree of design.
In addition, when flip-chip integrated circuit elements 109 are mounted on one of the outermost layers of this multilayer board and a motherboard (not shown) is connected to the outermost layer on the opposite side, the reliability of the connection between integrated circuit elements 109 and the multilayer board is poor. The reason for this poor reliability is the high degree of thermal stress that occurs between integrated circuit elements 109 and the multilayer board due to the great difference between the linear expansion coefficient of the built-up portion of the multilayer board (approximately 50 ppm in the direction of thickness and 14-16 ppm in the surface direction) and the linear expansion coefficient of the silicon that is the main material of integrated circuit elements 109 (3-4 ppm in the direction of thickness and 3-4 ppm in the surface direction).
On the other hand, a ceramic multilayer board such as was disclosed in Japanese Patent Application Laid-Open No. 2002-118194 does not allow green sheets of very thin construction. For example, when constructing a multilayer board having ten or more, or in particular, having thirteen or more layers, the thickness of the green sheets, which each have a thickness of, for example, 2 mm or more, complicates their use as a package for semiconductor devices.
In this example, conductive pattern 106 is formed by printing metal on a green sheet, following which the green sheet is sintered and cured. However, the final dimensional accuracy of conductive pattern 106 is poor in this fabrication method, and adequate control of the position of conductive pattern 106 to obtain the desired impedance is therefore extremely difficult.
In addition, when flip-chip integrated circuit elements 109 are mounted on one outermost layer of this multilayer board and a motherboard (not shown) is connected to the outermost layer on the opposite side, the reliability of the package connections are poor. This poor reliability results from the great difference between the linear expansion coefficient of the ceramic that is the main material of the multilayer board (4-6 ppm in the direction of thickness and 4-6 ppm in the surface direction) and the linear expansion coefficient of the glass epoxy resin that is the main material of the motherboard (16-17 ppm in the direction of thickness and 60 ppm in the surface direction). In addition, the semiconductor device package is subject to a high degree of stress. Further, the dielectric constant of a ceramic is higher than that of an organic material, and the loss of the high-frequency signal that passes through the conductive pattern is therefore great.
Japanese Patent Application Laid-open No. 2004-095963 discloses a multi-layer board comprising a thermoplastic polyimide sheet having a thermosetting characteristic and a glass transition point Tg which is lower than the curing start temperature Ts of a thermosetting component.
Japanese Patent Application Laid-open No. 2004-064009 discloses a method of manufacturing a printed circuit board wherein a plurality of slits are formed so as to surround a product region in each of laminated resin films. Further, Japanese Patent Application Laid-open No. 2003-318538 also discloses a method of manufacturing a printed circuit board wherein a plurality of slits are formed between product regions in each of laminated resin films.
Japanese Patent Application Laid-open No. 2003-324280 discloses a method of manufacturing a printed circuit board comprising thermoplastic resin sheets having a conductive pattern on one surface and a via hole on the other surface. Many thermoplastic resin sheets are laminated and simultaneously bonded each other and the conductive pattern is connected to the low melting point metal filled in the via hole by metallic bonding.
Japanese Patent Application Laid-open No. 2003-209356 discloses a method of manufacturing a multi-layer board wherein a plurality of through holes are formed in each of resin films so as to superpose each other in a laminating direction of the films and conductive paste is filled in the through holes. The conductive paste is sintered to form poles which support a hot pressing plate, when the laminated films are heated and pressurized.
Japanese Patent Application Laid-open No. 2003-273511 discloses a pressing method wherein a plurality of thermoplastic films having a conductive pattern on one surface are laminated and simultaneously bonded each other by heating and pressurization on the both sides with buffer members each of which is interposed between the outermost thermoplastic film and a thermal pressing plate.
“Microelectronics Packaging Handbook” by Rao R. Tummala, Eugene J. Rymaszewski, and Alan G. Klopfenstein, in particular pp. 375-411 of Japanese version, teaches various type of package, such as a ceramic chip carrier, a flat package, a hybrid package and a multi-layer ceramic substrate.